1Design Enhancements for In-Cache Computations

Abstract—New programming models and increased off-chip bandwidth demands of multicore processors have changed the nature of the memory wall problem, and in-novative hardware and software solutions are emerging to combat the resulting latency and power issues. Emerging processor designs include organizations of on-chip resources that diverge from the classical multicore model. One ex-ample of a such a system increases core counts along a new design dimension by embedding simple cores into the cache hierachy of more complex, conventional cores. Development of new execution models based on In-Cache Computations (ICCs) for execution on such a system is underway. This work presents several enhancements to the ICC design, in-cluding an improved style of execution, co-processor archi-tecture, and ICC code generation techniques. Simulation results highlight promising opportunities for significant ad-vantages over conventional architectures, including up to 61 % average improvement in L1 cache miss rate for a con-ventional host processor. We project an average potential speedup of 1.32 due to increased L1 hit rate allowed by ICCs. I