This paper presents an in-depth study of the theory and algorithms for the SPFD-based (Set of Pairs of Functions to be Distinguished) rewiring, and explores the flexibility in the SPFD computation. Our contributions are in the following two areas: (1) We present a theorem and a related algorithm for more precise characterization of feasible SPFD-based rewiring. Extensive experimental results show that for LUT-based FPGAs, the rewiring ability of our new algorithm is 70 % higher than SPFD-based local rewiring algorithms (SPFD-LR) [19][21] and 18 % higher than the recently developed SPFD-based global rewiring algorithm (SPFD-GR)[20]. (2) In order to achieve more rewiring ability on certain selected wires used in various optimizations, we stud...
This article presents a synthesis strategy aimed at minimizing the dynamic power consumption of comb...
[[abstract]]Generally, there exist random-pattern resistant faults that result in the poor fault cov...
Abstract — Modern SRAM-based field-programmable gate arrays (FPGAs) are prone to single event upsets...
u.ac.jp This paper proposes an innovative method for SPFD-based rewiring in Look-Up-Table-based (LUT...
AbstractIn this work, we implement a new rewiring based flow for FPGA performance improvement in pos...
[[abstract]]In this paper, we present a method to re-synthesize Look-Up Table (LUT) based Field Prog...
Yamashita et. al.[1] introduced a new category for ex-pressing the flexibility that a node can have ...
[[abstract]]This paper presents a very efficient optimization method suitable for multilevel combina...
SPFDs are a mechanism to express flexibility in Boolean networks. Introduced by Yamashita et al. in ...
University of Minnesota Ph.D. dissertation. December 2009. Major: Electrical Engineering. Advisor: D...
Abstract—Wire removal is a technique by which the total number of wires between individual circuit n...
This paper describes the application of an SPFD-based wire removal technique for circuit implementat...
Technology dependent logic optimization is usually carried through a sequence of design rewiring ope...
[[abstract]]This paper presents a very efficient Boolean logic optimization method. The boolean opti...
It is known that most field programmable gate array (FPGA) mapping algorithms consider only combinat...
This article presents a synthesis strategy aimed at minimizing the dynamic power consumption of comb...
[[abstract]]Generally, there exist random-pattern resistant faults that result in the poor fault cov...
Abstract — Modern SRAM-based field-programmable gate arrays (FPGAs) are prone to single event upsets...
u.ac.jp This paper proposes an innovative method for SPFD-based rewiring in Look-Up-Table-based (LUT...
AbstractIn this work, we implement a new rewiring based flow for FPGA performance improvement in pos...
[[abstract]]In this paper, we present a method to re-synthesize Look-Up Table (LUT) based Field Prog...
Yamashita et. al.[1] introduced a new category for ex-pressing the flexibility that a node can have ...
[[abstract]]This paper presents a very efficient optimization method suitable for multilevel combina...
SPFDs are a mechanism to express flexibility in Boolean networks. Introduced by Yamashita et al. in ...
University of Minnesota Ph.D. dissertation. December 2009. Major: Electrical Engineering. Advisor: D...
Abstract—Wire removal is a technique by which the total number of wires between individual circuit n...
This paper describes the application of an SPFD-based wire removal technique for circuit implementat...
Technology dependent logic optimization is usually carried through a sequence of design rewiring ope...
[[abstract]]This paper presents a very efficient Boolean logic optimization method. The boolean opti...
It is known that most field programmable gate array (FPGA) mapping algorithms consider only combinat...
This article presents a synthesis strategy aimed at minimizing the dynamic power consumption of comb...
[[abstract]]Generally, there exist random-pattern resistant faults that result in the poor fault cov...
Abstract — Modern SRAM-based field-programmable gate arrays (FPGAs) are prone to single event upsets...