Event model interfaces for heterogeneous system analysis

Complex embedded systems consist of hardware and software components from different domains, such as control and signal processing, many of them supplied by different IP vendors. The embedded system designer faces the challenge to integrate, opti-mize and verify the resulting heterogeneous systems. While for-mal verification is available for some subproblems, the analysis of the whole system is currently limited to simulation or emula-tion. In this paper, we tackle the analysis of global resource shar-ing, scheduling, and buffer sizing in heterogeneous embedded sys-tems. For many practically used preemptive and non-preemptive hardware and software scheduling algorithms of processors and busses, semi-formal analysis techniques are known. However, they cannot be used in system level analysis due to incompatibilities of their underlying event models. This paper presents a technique to couple the analysis of local scheduling strategies via an event in-terface model. We derive transformation rules between the most important event models and provide proofs where necessary. We use expressive examples to illustrate their application. 1