Interconnect layout optimization under higherorder RLC model

In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response. We propose a unified approach that considers topology optimization, wire-sizing optimization, and waveform optimization simultaneously. Our algorithm considers a large class of routing topologies, ranging from shortest-path Steiner trees to bounded-radius Steiner trees and Steiner routings. We construct a set of required-arrival-time Steiner trees or RATS-trees, providing a smooth trade-off among signal delay, wave-form, and routing area. Using a new incremental moment computation algorithm, we interleave topology construction with moment compu-tation to facilitate accurate delay calculation and evaluation of wave-form quality. Experimental results show that our algorithm is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot, and routing cost.