Circuit Size Optimization with Multiple Sources of Variation and Position Dependant Correlation

The growing impact of process variation on circuit performance requires statistical design approaches in which circuits are designed and optimized subject to an estimated variation. Previous work [1] has shown that by including extra margins in each of the gate delays and optimizing the gate sizes, the circuit delay variation can be reduced by half. Our work goes further by deploying extended models that include delay variations due to Vth and Leff, as well as position dependant variation. Two types of models have been proposed to account for various variations: 1) a model that explicitly adds spatial correlation terms to the design objective; 2) a model that implicitly includes such effect through the use of a modified version of Pelgrom’s model. These design models are used to size a 32-bit Ladner-Fischer adder and the circuit delay distributions are obtained from Monte Carlo simulations. The analysis shows that both types of models have a noticeable performance improvements over the model presented in [1]. In addition, the second model appears to be a more adequate method for modeling various variation components and has a better performance over the first model; the drawback is a more complicated object function