User-perceived Latency Driven Voltage Scaling for Interactive Applications ∗

Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as dynamic voltage scaling (DVS) and adaptive body biasing (ABB), have been shown to reduce energy consumption effectively. Previous works on DVS and ABB exploit low CPU utilization of the processor to drive volt-age scaling. This has become inadequate for modern interactive applications involving high CPU usage. In this work, we target computer responsiveness during voltage scaling to exploit more op-portunities for energy reduction. Instead of CPU utilization, we use the user-perceived latency, the delay between user input and com-puter response, to drive voltage scaling. Considering the tradeoff between energy consumption and computer responsiveness during voltage scaling not only reduces energy consumption effectively, but also ensures good computer responsiveness for interactive ap-plications. Experimental results show that for the 70nm technol-ogy, during the execution of seven commonly-used interactive ap-plications, the energy consumption of the processor using user-perceived latency driven DVS is reduced by an average of 37.3%, and the user-perceived latency by an average of 18.3%, compared to CPU utilization driven DVS. If both DVS and ABB are per-formed simultaneously based on the user-perceived latency, then the energy consumption is reduced by another 38.9 % compared to when DVS is performed alone, while maintaining a similar com-puter responsiveness level. We have implemented user-perceived latency driven voltage scaling under Linux with X Window sys-tem. However, the methodology is extensible to other operating systems as well