A case for integrated processor-cache partitioning in chip multiprocessors

Existing cache partitioning schemes are designed in a man-ner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an oper-ating system directed integrated processor-cache partition-ing scheme that partitions both the available processors and the shared cache in a chip multiprocessor among different multi-threaded applications. Extensive simulations using a set of multiprogrammed workloads show that our integrated processor-cache partitioning scheme facilitates achieving bet-ter performance isolation as compared to state of the art hardware/software based solutions. Specifically, our inte-grated processor-cache partitioning approach performs, on an average, 20.83 % and 14.14 % better than equal partition-ing and the implicit partitioning enforced by the underlying operating system, respectively, on the fair speedup metric on an 8 core system. We also compare our approach to pro-cessor partitioning alone and a state-of-the-art cache parti-tioning scheme and our scheme fares 8.21 % and 9.19 % better than these schemes on a 16 core system. 1