Minimum Delay Adder for Redundant Complex Binary Number System

Abstract: We find the applications of complex numbers in almost all fields of modern science and engineering. Due to its much application a lot of research work is underway to reduce the computation requirements for the Complex binary numbers. Recent research indicates that complex numbers can be represented in single binary-unit format as in Complex Binary Number System (CBNS) with bases (−1+j) and (−1−j). One-unit binary representation of complex numbers in CBNS form reduces computational complexity in arithmetic operations involving such numbers, although the problem of carry appears to be more pronounced in this system compared to base-2 binary system. This has led to the definition of Redundant Complex Binary Number System (RCBNS), which permits carry-free addition of complex binary numbers. This paper proposes an hardware architecture for the carry-free addition of RCBNS. The presented adder is developed directly from truth table of 3-bit block RCBNS addition