Design of FPGA Interconnect for Multilevel Metallization

How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third-dimension to reduce switch requirements. Unfortunately, traditional FPGA wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topology, based on Leighton’s Mesh-of-Trees, which care-fully exploits hierarchy to allow additional metal layers to support arbitrary device scaling. When wiring layers grow sufficiently fast with aggregate network size (N), our network requires only O(N) area; this is in stark contrast to tra-ditional, Manhattan FPGA routing schemes where switch-ing requirements alone grow superlinearly in N. In practice, we show that, even for the admittedly small designs in the Toronto “FPGA Place and Route Challenge, ” the Mesh-of-Trees networks require 10 % less switches than the standard, Manhattan FPGA routing scheme