A multi-core approach to addressing the energy-complexity problem

This paper proposes single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. It assumes a single chip containing a diverse set of cores that target different performance levels and consume different levels of power. During an applica-tion’s execution, system software evaluates the resources re-quired by an application for good performance and dynami-cally chooses the core that can best meet these requirements while minimizing energy consumption. It describes an ex-ample architecture with ve cores of varying performance and complexity. Initial results show a more than three-fold reduction in energy at a cost of only 18 % performance.