On-chip supply networks are playing an increasingly important role for modern nanometer-scale designs. However, the ever growing sizes of power grids make the analysis problem extremely difficult thereby introducing severe challenges in design and optimization. The inherent analysis complexity calls for innovations in simulation techniques that must provide appropriate accuracy, efficiency as well as the tradeoff thereof to aid design verification and optimization. In this paper, we first present a sampling-based sensitivity analysis by employing the notation of importance sampling in a Monte Carlo based circuit simulation framework. This technique allows the extraction of multi-parameter sensitivities for the node voltages of interest in t...
We propose a new technique called node sampling to speed up the probability-based power estimation m...
University of Minnesota Ph.D. dissertatation. August 2013. Major: Electrical Engineering. Advisor: S...
With the aggressive scaling down of semiconductor VLSI devicesfrom 65nm to 45 nm, 32nm, the process ...
Today, power consumption plays an important role in digital IC design. Demands come from the applica...
Abstract—Variations of process parameters have an important impact on reliability and yield in deep ...
Verifying the power grid requires checking if the voltage drops on all the nodes do not exceed the t...
Variations of process parameters have an important impact on reliability and yield in deep sub micro...
Abstract--In this paper, a unified theory for frequency-domain simula-tion and sensitivity analysis ...
Due to the statistical uncertainty of loads and power sources found in smart grids, effective comput...
The electronics industry provides the core technology for numerous industrial innovations. Progress ...
The ongoing trend from micro- to nanoelectronics causes the growth of the relative parameter variati...
The design and analysis of the power distribution and supply system on a chip is a complex issue. Th...
This dissertation presents stochastics-based methods enabling testing related to three different asp...
As the technology scales into 90nm and below, process-induced variations become more pronounced. In ...
As transistor dimensions of Static Random AccessMemory (SRAM) become smaller with each new technolog...
We propose a new technique called node sampling to speed up the probability-based power estimation m...
University of Minnesota Ph.D. dissertatation. August 2013. Major: Electrical Engineering. Advisor: S...
With the aggressive scaling down of semiconductor VLSI devicesfrom 65nm to 45 nm, 32nm, the process ...
Today, power consumption plays an important role in digital IC design. Demands come from the applica...
Abstract—Variations of process parameters have an important impact on reliability and yield in deep ...
Verifying the power grid requires checking if the voltage drops on all the nodes do not exceed the t...
Variations of process parameters have an important impact on reliability and yield in deep sub micro...
Abstract--In this paper, a unified theory for frequency-domain simula-tion and sensitivity analysis ...
Due to the statistical uncertainty of loads and power sources found in smart grids, effective comput...
The electronics industry provides the core technology for numerous industrial innovations. Progress ...
The ongoing trend from micro- to nanoelectronics causes the growth of the relative parameter variati...
The design and analysis of the power distribution and supply system on a chip is a complex issue. Th...
This dissertation presents stochastics-based methods enabling testing related to three different asp...
As the technology scales into 90nm and below, process-induced variations become more pronounced. In ...
As transistor dimensions of Static Random AccessMemory (SRAM) become smaller with each new technolog...
We propose a new technique called node sampling to speed up the probability-based power estimation m...
University of Minnesota Ph.D. dissertatation. August 2013. Major: Electrical Engineering. Advisor: S...
With the aggressive scaling down of semiconductor VLSI devicesfrom 65nm to 45 nm, 32nm, the process ...