Add to ORKGThis paper presents a method to automatically recog-nize and model single and multi-output logic gates out of a switch-level network, even for irregular transistor struc-tures. Result subcircuit models are directly used in a sym-bolic simulator for circuit analysis purposes. Other appli-cations of derived netlists cover switch-level simulation ac-celeration and test generation tool enhancement. 1
Describing integrated circuits based on their physical and topological properties leads naturally to...
Abstract − The paper deals with a symbolic simulator we have developed. It has been used as a suppor...
In the fields of power electronics and power systems, the modeling and simulation of switching conve...
The switch-level model describes the logical behavior of digital systems implemented in metal oxide ...
The switch-level model describes the logical behavior of digital circuits implemented in metal ox...
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The result...
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resul...
The program MOSSYM simulates the behavior of a MOS circuit represented as a switch-level network sym...
Thls thesis presents an algorithm for fault simulation of metal-oxide-semiconductor (MOS), field-eff...
In this dissertation, the use of extracted functional models in some typical Computer-Aided-Design a...
Switch-level simulation has become an indispensable tool in the verification of large MOS circuits. ...
This paper describes an algorithm for the simulation of gate-level logic. Multiple logic levels are ...
The paper describes a new technique for extracting clock level finite state machines (FSMs) from tra...
INTRODUCTION This manual is meant as a guide to users who want to simulate their network with the s...
Circuit Simulation is a critical bottleneck in VLSI design. This paper describes a parallel switch-l...
Describing integrated circuits based on their physical and topological properties leads naturally to...
Abstract − The paper deals with a symbolic simulator we have developed. It has been used as a suppor...
In the fields of power electronics and power systems, the modeling and simulation of switching conve...
The switch-level model describes the logical behavior of digital systems implemented in metal oxide ...
The switch-level model describes the logical behavior of digital circuits implemented in metal ox...
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The result...
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resul...
The program MOSSYM simulates the behavior of a MOS circuit represented as a switch-level network sym...
Thls thesis presents an algorithm for fault simulation of metal-oxide-semiconductor (MOS), field-eff...
In this dissertation, the use of extracted functional models in some typical Computer-Aided-Design a...
Switch-level simulation has become an indispensable tool in the verification of large MOS circuits. ...
This paper describes an algorithm for the simulation of gate-level logic. Multiple logic levels are ...
The paper describes a new technique for extracting clock level finite state machines (FSMs) from tra...
INTRODUCTION This manual is meant as a guide to users who want to simulate their network with the s...
Circuit Simulation is a critical bottleneck in VLSI design. This paper describes a parallel switch-l...
Describing integrated circuits based on their physical and topological properties leads naturally to...
Abstract − The paper deals with a symbolic simulator we have developed. It has been used as a suppor...
In the fields of power electronics and power systems, the modeling and simulation of switching conve...