So far, the privileged instructions MONITOR and MWAIT introduced with Intel Prescott core, have been used mostly for inter-thread synchronization in operating systems code. In a hyper-threaded processor, these instructions offer a “performance-optimized ” way for threads involved in synchronization events to wait on a condition. In this work, we explore the potential of using these instructions for synchronizing application threads on hyper-threaded processors which are characterized by workload imbalance. Initially, we propose a framework through which one can use MONITOR/MWAIT to build condition wait and notification primitives, with minimal kernel involvement. Then, we evaluate the efficiency of these primitives in an incremental manner:...
International audienceIn modern operating systems and programming languages adapted to multicore com...
Parallel workloads most commonly execute onto pools of thread, allowing to dispatch and run individu...
Large, high frequency single-core chip designs are increasingly being replaced with larger chip mult...
Existing multiprocessor synchronization mechanisms are relatively heavyweight, due in part to the le...
As thread level parallelism in applications has continued to expand, so has research in chip multi-c...
For most multi-threaded applications, data structures must be shared between threads. Ensuring threa...
With the proliferation of Chip Multiprocessors (CMPs), shared memory multi-threaded programs are exp...
Abstract This paper proposes and evaluates new synchronization schemes for a simultaneous multithrea...
Available computing power in modern computers has been steadily increasing in the form of processor ...
Speculative parallelization (SP) enables a processor to extract multiple threads from a sequential i...
The performance of thread mechanism is dominated primarily by two kinds of thread-switching overhead...
Analyzing multi-threaded programs is quite challenging, but is necessary to obtain good multicore pe...
: Traditional compilation techniques for synchronization have targeted architectures with relatively...
Multi-core processors are ubiquitous. Even embedded systems nowadays use processors with multiple co...
The design of microprocessors is undergoing radical changes that affect the performance and reliabil...
International audienceIn modern operating systems and programming languages adapted to multicore com...
Parallel workloads most commonly execute onto pools of thread, allowing to dispatch and run individu...
Large, high frequency single-core chip designs are increasingly being replaced with larger chip mult...
Existing multiprocessor synchronization mechanisms are relatively heavyweight, due in part to the le...
As thread level parallelism in applications has continued to expand, so has research in chip multi-c...
For most multi-threaded applications, data structures must be shared between threads. Ensuring threa...
With the proliferation of Chip Multiprocessors (CMPs), shared memory multi-threaded programs are exp...
Abstract This paper proposes and evaluates new synchronization schemes for a simultaneous multithrea...
Available computing power in modern computers has been steadily increasing in the form of processor ...
Speculative parallelization (SP) enables a processor to extract multiple threads from a sequential i...
The performance of thread mechanism is dominated primarily by two kinds of thread-switching overhead...
Analyzing multi-threaded programs is quite challenging, but is necessary to obtain good multicore pe...
: Traditional compilation techniques for synchronization have targeted architectures with relatively...
Multi-core processors are ubiquitous. Even embedded systems nowadays use processors with multiple co...
The design of microprocessors is undergoing radical changes that affect the performance and reliabil...
International audienceIn modern operating systems and programming languages adapted to multicore com...
Parallel workloads most commonly execute onto pools of thread, allowing to dispatch and run individu...
Large, high frequency single-core chip designs are increasingly being replaced with larger chip mult...