Circuit Design of DRAM for Mobile Generation

Abstract—In recent few years, low-power electronics has been a leading drive for technology developments nourished by rapidly growing market share. Mobile DRAM, as a fundamental block of hand-held devices, is now becoming a product developed by limitless competition. To support application specific mobile features, various new power-reduction schemes have been proposed and adopted by standardization. Tightened power budget in battery-operated systems makes conventional schemes not acceptable and increases difficulty of the circuit design. The mobile DRAM has successfully moved down to 1.5V era, and now it is about to move to 1.2V. Further voltage scaling, however, presents critical problems which must be overcome. This paper reviews critical issues in mobile DRAM design and various circuit schemes to solve the problems. Focused on analog circuits, bit-line sensing, IO line sensing, refresh-related schemes, DC bias generation, and schemes for higher data rate are covered. Index Terms—Low-power DRAM, refresh, temper