Elastic Timing Scheme for Energy-Efficient and Robust Performance

In nanometer regime, IC designers are struggling between sig-nificant variation effects and tight power constraints. The con-ventional approach- using timing safety margin, consumes power continuously to guard against low probability timing variations. Such power inefficiency is largely eliminated in the Razor tech-nology which detects and corrects variation induced timing er-rors at runtime. However, the error correction scheme of Razor causes pipeline stalling/flushing and therefore is not preferred in real-time systems or sequential circuits with feedback loops. We propose an elastic timing scheme which can correct timing er-rors without stalling/flushing pipeline. This is achieved by dynam-ically boosting circuit speed when timing error occurs. A dynamic clock skew shifting technique is suggested to reduce the boosting cost. An optimization algorithm is also provided to minimize the cost overhead. Compared to conventional safety margin based ap-proach, the elastic timing scheme can reduce power dissipation by 20 % − 27 % on ISCAS89 sequential circuits while retaining simi-lar variation tolerance. After optimization, the boosting is needed for only a small portion of entire circuit. As a result, the area overhead is usually less than 5%.