A FLEXIBLE ARCHITECTURE FOR DSP APPLICATIONS COMBINING HIGH PERFORMANCE ARITHMETIC WITH SMALL SCALE CONFIGURABILITY

This paper presents the architecture of a flexible and high performance unit for DSP applications. The proposed archi-tecture operates based on fast Carry-Save (CS) arithmetic. A mapping methodology, for datapaths composed with the pro-posed flexible units, is also presented. It exploits the incorpo-rated features of the proposed units and enables fast compu-tations, high operation densities and advanced data reusabil-ity. Experimental results shown that several DSP algorithms can be mapped onto the proposed architecture with high ef-ficiency delivering in average, latency gains of 36.56 % and 45.76 % compared to the MAC and the primitive resources based datapaths, respectively. 1