Behavioral synthesis methodology for HDLbased specification and validation

This paper describes a HDL synthesis based design methodology that supports user adoption of behavioral-level synthesis into normal design practices. The use of these techniques increases understanding of the HDL descriptions before synthesis, and makes the comparison of pre- and post-synthesis design behavior through simulation much more direct. This increases user confidence that the specification does what the user wants, i.e. that the synthesized design matches the spec-ification in the ways that are important to the user. At the same time, the methodology gives the user a powerful set of tools to specify com-plex interface timing, while preserving a user’s ability to delegate decision-making authority to software in those cases where the user does not wish to restrict the options available to the synthesis algo-rithms. 1.0 Overvie