Design of High Speed I/O Interfaces for High Performance Microprocessors

Advances in CMOS process technology have enabled high performance micropro-cessors that run multiple threads in parallel at multi-gigahertz clock frequencies. The off-chip input/output (I/O) bandwidth of these chips should scale along with the on-chip computation capacity in order for the entire system to reap performance benefits. However, scaling of off-chip I/O bandwidth is constrained by limited physical pin re-sources, legacy interconnect technology and increasingly noisy on-chip environment. Limited power budgets and process/voltage/temperature (PVT) variations present additional challenges to the design of I/O circuits. This thesis focuses on the need to improve timing margin at the data samplers in the receivers, to enable higher symbol-rates per channel. The first part of this thesis describes a technique to reclaim timing margin lost to jitter both in the transmitted data and sampling clock. The second part discusses two techniques to correct for static phase errors in the sampling clocks that can degrade timing margin. Two test-chips, designed and fabricated in 0.13µm CMOS technology, demonstrate the efficac