ACCELERATION IN PROGRAMMABLE MULTI-STANDARD BASEBAND PROCESSORS

Programmability will be increasingly important in future multi-standard radio systems. We are proposing an ar-chitecture for fully programmable baseband processing, based on a programmable DSP processor and a num-ber of congurable accelerators which communicate via a congurable network. Acceleration of common cycle-consuming DSP jobs is necessary in order to manage wide-band modulation schemes. In this paper we inves-tigate which jobs are suitable for acceleration in a pro-grammable baseband procsessor supporting a number of common Wireless LAN and 3G standards. Benchmark-ing show that with the proposed set of accelerators, our architecture can support the discussed standards, includ-ing IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz