Automated synthesis of digital multiplexer networks A.E.A. Almaini, PhD, FlEE

Abstract: A programmed algorithm is presented for the synthesis and optimisation of networks implemented with multiplexer universal logic modules. The algorithm attempts level by level optimisation selecting the control variables that result in minimum number of continuing branches. Cascaded networks, if realisable, are always found and given preference over tree net-works, though mixtures of cascade and tree con-figurations are permitted. The algorithm is programmed in Fortran and tested for single and double control variable modules. In theory, the program can be used for any number of variables for completely and incompletely specified func-tions.