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state.edu GPUs are a class of specialized parallel architectures with tremen-dous computational power. The new Compute Unied Device Ar-chitecture (CUDA) programming model from NVIDIA facilitates programming of general purpose applications on their GPUs. How-ever, manual development of high-performance parallel code for GPUs is still very challenging. In this paper, a number of issues are addressed towards the goal of developing a compiler frame-work for automatic parallelization and performance optimization of afne loop nests on GPGPUs: 1) approach to program transfor-mation for efcient data access from GPU global memory, using a polyhedral compiler model of data dependence abstraction and program transformation; 2) determination of optimal padding fac-tors for conict-minimal data access from GPU shared memory; and 3) model-driven empirical search to determine optimal param-eters for unrolling and tiling. Experimental results on a number of kernels demonstrate the effectiveness of the compiler optimization approaches developed