A Novel Multiple Core Co-Processor Architecture for Efficient Server-based

We present an SoC-based cryptographic co-processor for server applications, which supports different public key cryptographic schemes. Its novel architecture comprises multiple cores and utilizes HW/SW co-design to support flexibility concerning the supported cryptographic schemes. The emphasis on servers shifts the focus to high throughput, while the usual metric in literature is low latency. Thus, to gain low latency, usual architectures feature high par-allelization at the lowest abstraction level leading to some limitations regarding the throughput, if used to support dif-ferent schemes. Consequently, the proposed architecture utilizes parallelization at this level only to a low degree and compensates the resulting loss in efficiency by heavily ex-ploiting parallelization at higher abstraction levels. 1