Lithography Independent Fabrication of Nano-MOS-Transistors with

The 2001 update of the International Technology Roadmap for Semiconductors predicts a printed minimum MOS-transistor channel length of 13 nm for the year 2016, which results in a physical gate length of only 9 nm [1]. The resolution of optical lithography still dramatically increases, but known and proved solutions for structure sizes significantly below 100 nm do not exist up to now. This paper presents a new method for the fabrication of extremely small MOS-transistors with a channel area down to W = 25 nm and L = 25 nm with low demands to the used lithography. It is based on our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, while the channel width was not scaled. The used technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size