Shared Reconfigurable Architectures for CMPs

This paper investigates reconfigurable architectures suit-able for chip multiprocessors (CMPs). Prior research has established that augmenting a conventional processor with reconfigurable logic can dramatically improve the perfor-mance of certain application classes, but this comes at non-trivial power and area costs. Given substantial observed time and space differences in fabric usage, we propose that pools of programmable logic should be shared among mul-tiple cores. While a common shared pool is more compact and power efficient, fabric conflicts may lead to large per-formance losses relative to per-core private fabrics. We identify particular characteristics of past reconfig-urable fabric designs that are particularly amenable to fabric sharing. We then propose spatially and temporally shared fabrics in a CMP. The sharing policies that we devise in-cur negligible performance loss compared to private fabrics, while cutting the area and peak power of the fabric by 4X. 1