Network Interface Sharing Techniques for Area Optimized NoC Architectures

Although preliminary analysis frameworks point out the performance speed-ups achievable by on-chip networks with respect to state-of-the-art interconnects, the area con-cern remains one of the most daunting challenges to make this interconnect technology mainstream. A common ap-proach to relieve the problem consists of sharing most of network interface resources among a number of processor cores. However, buffering resources need to be replicated and control logic reaches a complexity that limits maximum achievable frequency. This paper proposes full sharing of network interface resources, including buffers, thus trading performance for area. While area improvements are signif-icant, a number of physical and system-level effects might mitigate performance degradation, making our technique a promising solution for area efficient network-on-chip real-izations across a range of operating conditions.