Robust differential asynchronous nanoelectronic circuits

Abstract — Nanoelectronic design faces unprecedented relia-bility challenges and must achieve noise immunity and delay in-sensitiveness in the presence of prevalent defects and significant parametric variations. Asynchronous circuits have the great po-tential to achieve delay insensitive, high performance and low power nanoelectronic design, while the existing asynchronous cir-cuits do not guarantee logic and timing correctness in the pres-ence of glitches. In this paper, I propose robust differential asyn-chronous (RDA) circuits, which combine asynchronous circuits for delay insensitiveness, differential logic for redundancy, and er-ror detection codes for resilience. Theoretical analysis and SPICE simulation based on 22nm CMOS Predictive Technology Models show that the proposed RDA circuits achieve much enhanced reli-ability in (1) logic correctness at the event of a single bit soft error or common multiple bit soft errors by differential logic and error detection codes, and (2) timing correctness for any delay variation given physical proximity of the circuit components, with compa-rable area overhead to existing asynchronous circuits. I