Trading Off Dependability and Cost for Nanoscale High Performance Microprocessors: The Clock Distribution Problem

The continuous scaling of microelectronics technology allows for keeping on increasing IC performance and complexity, but simultaneously poses serious challenges to design, test and dependability. For high performance microprocessors, guaranteeing that clock signals are distributed throughout the die with correct skew, duty-cycle, limited jitter and sharp edges is becoming ever more challenging, and is expected to get even worse for next generation microprocessors. On the other hand, the availability of correct clock signals throughout the die is mandatory for their dependable operation. This problem will be described and possible approaches for dependable clock signal distribution will be discussed. Extended Summary The continuous scaling of microelectronics technology allows for keeping on increasing IC performance and complexity, but simultaneously poses serious challenges to design, test and dependability. Manufacturing defects are becoming more likely, and parameter variations occurring during fabrication even more severe. Together with the increased ICs ' complexity and operating frequency, this is making ever more challenging to guarantee that clock signals are distributed throughout the die with correct skew, duty-cycle, limited jitter and sharp edges, although providing correct clock distribution is mandatory for synchronous ICs ’ dependable operation. Particularly, this is the case for high performance microprocessors and their clock distribution network (Fig. 1), whose signals are increasingly likely to get affected by faults, either directly involving clock nets [1], or their buffers [2]