Many different factors, such as topology, routing technique, selection function, flow control policy, complexity of router design, contribute to the performance of networks on chip (NoCs). Among these factors, the choice of topology and routing function has a significant effect on the average packet latency and saturation behavior. Torus is popular in many application domains, while the problem of virtual channel misbalance caused by its deadlock avoidance scheme brings lots of performance pathologies. In this paper, we present a novel deadlock avoidance scheme based on draining scheme, and propose a deadlock-free routing scheme for torus networks. We quantify the effects of the proposed routing scheme on the overall network performance by ...
This paper consists of two parts. In the first part, a new algorithm for deadlock- and livelock-free...
Minimizing latency and power are key goals in the design of NoC routers. Different proposals combine...
A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-...
In our previous work, a multi-path routing (MPR) scheme was proposed to maximize the data throughput...
A Hierarchical Torus Network (HTN) is a 2D-torus network of multiple Basic Modules (BM), in which th...
In this paper, we present a deadlock-free routing algorithm for the hierarchical torus network (HTN)...
TORUS is a n-dimensional network topology. Each dimension will have k nodes. A routing algorithm de...
International audienceNetworks-on-Chips (NoCs) are considered to be the paradigm of choice for on-ch...
The overall performance of Network-on-Chip (NoC) is strongly affected by the efficiency of the on-ch...
There is a seemingly endless miniaturization of electronic components, which has enabled designers t...
Interconnection networks play a crucial role in the performance of massively parallel computers. Hie...
Interconnection networks play a crucial role in the performance of massively parallel computers. Hie...
A hierarchical torus network (HTN) is a 2D-torus network of multiple basic modules, in which the bas...
In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as...
With the increasing capacity of FPGAs following the Moore's law, it is possible to build in a single...
This paper consists of two parts. In the first part, a new algorithm for deadlock- and livelock-free...
Minimizing latency and power are key goals in the design of NoC routers. Different proposals combine...
A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-...
In our previous work, a multi-path routing (MPR) scheme was proposed to maximize the data throughput...
A Hierarchical Torus Network (HTN) is a 2D-torus network of multiple Basic Modules (BM), in which th...
In this paper, we present a deadlock-free routing algorithm for the hierarchical torus network (HTN)...
TORUS is a n-dimensional network topology. Each dimension will have k nodes. A routing algorithm de...
International audienceNetworks-on-Chips (NoCs) are considered to be the paradigm of choice for on-ch...
The overall performance of Network-on-Chip (NoC) is strongly affected by the efficiency of the on-ch...
There is a seemingly endless miniaturization of electronic components, which has enabled designers t...
Interconnection networks play a crucial role in the performance of massively parallel computers. Hie...
Interconnection networks play a crucial role in the performance of massively parallel computers. Hie...
A hierarchical torus network (HTN) is a 2D-torus network of multiple basic modules, in which the bas...
In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as...
With the increasing capacity of FPGAs following the Moore's law, it is possible to build in a single...
This paper consists of two parts. In the first part, a new algorithm for deadlock- and livelock-free...
Minimizing latency and power are key goals in the design of NoC routers. Different proposals combine...
A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-...