Fast FIR Filters for SIMD Processors With Limited Memory Bandwidth

FIR filtering is one of the most populars DSP algorithms. Finite impulse response filters are easy to design, unconditionally stable, phase linearity is easily obtained. Also noise and rounding error analysis are easy. On the other hand FIR filters require high filter order when compared to IIR ones. It means increased number of multiplicatons and additions, and – what is also important – number of memory reads. Current processors and especially their SIMD units like AltiVec or SSE can perform FIR calculation much faster than memory controller can supply the data. Then reordering of calculations without changing the amount of them, gives significant algorithm speedup. In the paper the idea of FIR reordering is presented, followed by experimental results obtained on PowerPC G4 processor with AltiVec SIMD unit. 1. FIR FILTERS ON SIMD PROCESSORS FIR filtering, or digital convolution is a common operation in DSP area. Because of its simplicity it can be easily implemented on SIMD type of processors. Parallelization itself, while it is easily applied to FIR filters, is not enough to squeeze the maximum performance from a processor. The classic definition of computation complexity takes into account only number of arithmetic operations, usually in term