Scalable highthroughput SRAM-based architecture for IP-lookup using FPGA

Most high-speed Internet Protocol (IP) lookup implemen-tations use tree traversal and pipelining. However, this ap-proach results in inefficient memory utilization. Due to avail-able on-chip memory and pin limitations of FPGAs, state-of-the-art designs on FPGAs cannot support large routing ta-bles arising in backbone routers. Therefore, ternary content addressable memory (TCAM) is widely used. We propose a novel SRAM-based linear pipeline architecture, named DuPI. Using a single Virtex-4, DuPI can support a routing table of up to 228K prefixes, which is 3 × the state-of-the-art. Our architecture can also be easily partitioned, so as to use ex-ternal SRAM to handle even larger routing tables (up to 2 M prefixes), while maintaining a 324 MLPS throughput. The use of SRAM (instead of TCAM) leads to orders of magni-tude of reduction in power dissipation. Employing caching to exploit Internet traffic locality, we can achieve a through-put of 1.3 GLPS (billion lookups per second). Our design also maintains packet input order, and supports in-place non-blocking route updates. 1