The Synchronous Dataflow (SDF) model of computation is popu-lar for modelling the timing behaviour of real-time embedded hard-ware and software systems and applications. It is an essential in-gredient of several automated design-flows and design-space explo-ration tools. The model can be analysed for throughput and latency properties. Although the SDF model is fairly simple, the analysis algorithms are often of high complexity and the models that need to be analysed may be fairly large. This paper introduces two graph transformations for reducing large SDF graphs into simpler, smaller ones that can be analysed more efficiently and give a conservative and often tight estimation of the timing of the original model and hence of the hard real-t...