A Low Power, Single Chip Realization of a LowSpeed, Low-Delay CELP Coder/Decoder for Indoor Wireless Systems

Modulation (ADPCM) is a widely accepted high quality speech coding algorithm. Single chip devices exist for 32 kb/s ADPCM. "his algorithm requires a relatively large bandwidth and does not perform exceptionally well in noisy wireless environments, The 16 kb/s lowdelay code escited linear prediction (LD-CELP) coding algoritbm does perform well in misy environments and requires a reduced bandwidth. Tbrougb algorithm optimization and simulated verification of mixed analog and digital VLSI partitioning a single chip implementing tbe 16 kb/s LD-CELP voice coding algorithm will be possible. The performance of this coder chip will be comparable to the quality of 32 kb/s ADPCM. In this paper we propose the use of a link between Comdisco's SPW and Synopsis to determine tbe hardware related performance degradation and the tecbnologyl complexity related power dissipation and a m parameters. It will botb prove the concept of desige and determine tbe VLSI implementation feasibility. I