Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints

In this paper, a method for the automatic sizing of ana-log integrated circuits is presented. Basic sizing rules, re-presenting circuit knowledge, are set up before the sizing and are introduced as structural constraints into the sizing process. Systematic consideration of these structural con-straints during the automatic sizing prevents pathologically sized circuits and speeds up the automatic sizing. The siz-ing is done with a sensitivity-based, iterative trust region method.