A DSP Core for Telecommunication Applications

In this paper, design of an efficient DSP core for telecommunication applications is reported. Time and area consuming, the DSP processor is a critical component of the overall architecture, which is optimized for execution of signal processing operations. The goal is composing an optimized hardware appropriate for executing the considered instruction set. To accomplish this goal, the required architecture has been modeled, verified and synthesized using Verilog description and synthesis tools, including ModelSim, Leonardo spectrum and FPGA Advantage of Mentor Graphics. This DSP processor is implemented as an ASIC in TSMC 0.25 micron technology. 1