Time predictable CPU and DMA shared memory access

In this paper, we propose a first step towards a time pre-dictable computer architecture for single-chip multipro-cessing (CMP). CMP is the actual trend in server and desk-top systems. CMP is even considered for embedded real-time systems, where worst-case execution time (WCET) estimates are of primary importance. We attack the prob-lem ofWCET analysis for several processing units access-ing a shared resource (the main memory) by support from the hardware. In this paper, we combine a time predictable Java processor and a direct memory access (DMA) unit with a regular access pattern (VGA controller). We an-alyze and evaluate different arbitration schemes with re-spect to schedulability analysis and WCET analysis. We also implement the various combinations in an FPGA. An FPGA is the ideal platform to verify the different concepts and evaluate the results by running applications with in-dustrial background in real hardware. 1