Categories and Subject Descriptors

We propose a low-power two-port SRAM suitable for real-time video processing. In order to minimize discharge power on a read bitline, a majority-logic decides if input data are inverted in a write cycle, so that “1”s are in the majority. In video data, since more significant bits of adjacent pixel data are fortunately lopsided to either “0 ” or “1 ” with higher probability, the data bits in the pixels are reordered in each digit group to exploit the majority logic. The speed and area overheads are 4 % and 11 % in a 90-nm process technology, respectively. The proposed SRAM achieves 53 % power reduction on the bitlines, and saves 43 % of a total power when considered as an H.264 reconstructed-image memory