Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs

This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed in [12], but instead of using the replication and re-optimization, it takes force of the classical iterative improvement parti-tioning techniques ([4],[14]). The basic effort consists in guiding the classical algorithms in their solution space ex-ploration. This was done by introducing the cost function based on the infeasibility distance of the partitioning solu-tion and carefully tuning the basic parameters of classical algorithms such as definition of size constraints for feasi-ble moves, handling solutions stack, selecting best cluster to move, etc. The proposed method obtains results com-parable to the best published results ([12],[16]), and even outperforms them for biggest benchmarks. 1