Add to ORKGAs the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become an inevitable issue for high-performance microprocessor designs. Since on-chip caches are major contributors of the leakage, a number of researchers have proposed efficient leakage reduction techniques. However, it is still not clear that 1) what kind of algorithm can be considered and 2) how much they have impact on energy and performance. To answer these questions, we explore run-time cache management algorithm, and evaluate the energy-performance efficiency for several alternatives. Key words: Low power, cache, leakage
Decreasing power consumption in small devices such as handhelds, cell phones and high-performance pr...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Energy management is important for a spectrum of systems ranging from high-performance architectures...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
A number of techniques to reduce cache leakage have so far been proposed. However, it is not clear t...
On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature ...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
Recently, energy dissipation by microprocessors is getting larger, which leads to a serious problem ...
fraction of the total power consumption of microprocessors. In nanometer-scale technology, the subth...
Leakage power is becoming dominant part of the micro-processor chip power budget as feature size shr...
Recent studies have shown that peripheral circuits, including decoders, wordline drivers, input and ...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is ...
Decreasing power consumption in small devices such as handhelds, cell phones and high-performance pr...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Energy management is important for a spectrum of systems ranging from high-performance architectures...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
A number of techniques to reduce cache leakage have so far been proposed. However, it is not clear t...
On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature ...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
Recently, energy dissipation by microprocessors is getting larger, which leads to a serious problem ...
fraction of the total power consumption of microprocessors. In nanometer-scale technology, the subth...
Leakage power is becoming dominant part of the micro-processor chip power budget as feature size shr...
Recent studies have shown that peripheral circuits, including decoders, wordline drivers, input and ...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is ...
Decreasing power consumption in small devices such as handhelds, cell phones and high-performance pr...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Energy management is important for a spectrum of systems ranging from high-performance architectures...