Fast Comparisons of Circuit Implementations ∗

Digital designs can be mapped to different implemen-tations using diverse approaches, with varying cost crite-ria. Post-processing transforms, such as transistor sizing can drastically improve circuit performance, by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the attainable circuit delay can be determined only after run-ning the tool. In this paper, we present an approach for fast transistor sizing that can enable a designer to choose one among several functionally identical implementations. Our algorithm computes the minimum achievable delay of a cir-cuit with a maximum average error of 5.5 % in less than a second for even the largest benchmarks.