Coarse-grained reconfigurable architectures have be-come increasingly important in recent years. Automatic design or compilation tools are essential to their success. In this paper, we present a modulo scheduling algorithm to exploit loop-level parallelism for coarse-grained recon-figurable architectures. This algorithm is a key part of our Dynamically Reconfigurable Embedded Systems Com-piler (DRESC). It is capable of solving placement, schedul-ing and routing of operations simultaneously in a modulo-constrained 3D space and uses an abstract architecture rep-resentation to model a wide class of coarse-grained archi-tectures. The experimental results show high performance and efficient resource utilization on tested kernels.
Modulo scheduling is a popular technique to enable pipelined execution of successive loop iterations...
The resource-constrained modulo scheduling problem is motivated by the 1-periodic cyclic instruc-tio...
Coarse-grained reconfigurable architectures, which offer massive parallelism coupled with the capabi...
Reconfigurable systems have drawn increasing attention from both academic researchers and creators o...
In high-end embedded systems, coarse-grained reconfigurable ar-chitectures (CGRA) continue to replac...
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by provid...
code generation, modulo scheduling, software pipelining, instruction scheduling, register allocation...
High-Level Synthesis tools have been increasingly used within the hardware design community to bridg...
Abstract—Dynamic scheduling algorithms have been success-fully used for parallel computations of nes...
Abstract: It is widely known that bandwidth limitations degrade parallel systems ’ performance. This...
Software pipelining is an important instruction scheduling technique for efficiently overlapping suc...
International audienceIn this paper, we focus on the resource-constrained modulo scheduling problem,...
Coarse-Grained Reconfigurable Architectures (CGRAs) are a promising solution to domain-specific appl...
Today the most commonly used system architectures in data processing can be divided into three categ...
Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variet...
Modulo scheduling is a popular technique to enable pipelined execution of successive loop iterations...
The resource-constrained modulo scheduling problem is motivated by the 1-periodic cyclic instruc-tio...
Coarse-grained reconfigurable architectures, which offer massive parallelism coupled with the capabi...
Reconfigurable systems have drawn increasing attention from both academic researchers and creators o...
In high-end embedded systems, coarse-grained reconfigurable ar-chitectures (CGRA) continue to replac...
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by provid...
code generation, modulo scheduling, software pipelining, instruction scheduling, register allocation...
High-Level Synthesis tools have been increasingly used within the hardware design community to bridg...
Abstract—Dynamic scheduling algorithms have been success-fully used for parallel computations of nes...
Abstract: It is widely known that bandwidth limitations degrade parallel systems ’ performance. This...
Software pipelining is an important instruction scheduling technique for efficiently overlapping suc...
International audienceIn this paper, we focus on the resource-constrained modulo scheduling problem,...
Coarse-Grained Reconfigurable Architectures (CGRAs) are a promising solution to domain-specific appl...
Today the most commonly used system architectures in data processing can be divided into three categ...
Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variet...
Modulo scheduling is a popular technique to enable pipelined execution of successive loop iterations...
The resource-constrained modulo scheduling problem is motivated by the 1-periodic cyclic instruc-tio...
Coarse-grained reconfigurable architectures, which offer massive parallelism coupled with the capabi...