1 PAPER Special Section on VLSI Technology toward Fronties of New Market Architectural-Level Soft-Error Modeling for Estimating Reliability

SUMMARY This paper proposes a soft-error model for accurately esti-mating reliability of a computer system at the architectural level within rea-sonable computation time. The architectural-level soft-error model identi-fies which part of memory modules are utilized temporally and spatially and which single event upsets (SEUs) are critical to the program execu-tion of the computer system at the cycle accurate instruction set simulation (ISS) level. The soft-error model is capable of estimating reliability of a computer system that has several memory hierarchies with it and finding which memory module is vulnerable in the computer system. Reliability estimation helps system designers apply reliable design techniques to vul-nerable part of their design. The experimental results have shown that the usage of the soft-error model achieved more accurate reliability estimation than conventional approaches. The experimental results demonstrate that reliability of computer systems depends on not only soft error rates (SERs) of memories but also the behavior of software running in computer systems