Test compression and hardware decompression for scan-based SoCs

Abstract.We present a new decompression architecture suitable for embedded cores in SoCs which focuses on im-proving the download time by avoiding higher internal-to-ATE clock ratios and by exploiting hardware paral-lelism. The Bounded Huffman compression facilitates decompression hardware tradeoffs. Our technique is scal-able in that the downloadable RAM-based decode table and accommodates for different SoC cores with different characteristics such as the number of scan chains and test set data distributions.