Improving the recursive multiplier

This paper examines the recursive multiplier and some potential enhancements f o r it. The delay of the recursive multiplier is similar to D a M a l l a c e fast multipliers, but the complexity is higher: Since the increase in complexity. comes from the reduction stages, modified reduction cells are dejined and compared to the existing design. The mod-$cations take advantage of the fact that some of the inputs in the reduction cells are not used Because of the simplic-ity of array multipliers in comparing gates and delays, most of the comparisons were done with the array multi-plier: Based on the original recursive multiplier; a diflerent implementation of the recursive multiplier is presented which has a “Dadda-like ’ ’ structure, but has greater regu-larity since it is based on the initial base multiplier struc-ture. The complexity is lower for the new design than the original recursive multipliel: Problem Dadda or Wallace fast multipliers provide high speed in calculations but they are difficult to layout because of their irregularity which also leads to larger area. Array multipli-ers (which may implement the modified Booth algorithm) have good regularity but do not have the speed of the fast multipliers. The recursive fast multiplier provides an inter-esting alternative because its performance is similar to a Dadda or a Wallace multiplier but it still maintains regular-ity. The problem associated with this method is its high complexity. This paper investigates the impact of the design of the base multiplier in the overall design and explores methods to reduce the complexity