The current literature offers two extremes of nonblocking software synchronization support for concurrent data struc-ture design: intricate designs of specific structures based on single-location operations such as compare-and-swap (CAS), and general-purpose multilocation transactional memory im-plementations. While the former are sometimes efficient, they are invariably hard to extend and generalize. The lat-ter are flexible and general, but costly. This paper aims at a middle ground: reasonably efficient multilocation operations that are general enough to reduce the design difficulties of algorithms based on CAS alone. We present an obstruction-free implementation of an atomic k-location-compare single-swap (KCSS) operation. KCSS allows f...
Atomic lock-free multi-word compare-and-swap (MCAS) is a powerful tool for designing concurrent algo...
Abstract: "An important class of concurrent objects are those that are lock-free, that is, whose ope...
Algorithms designed for current and future multi-core sys-tems, which are expected to experience an ...
Abstract. Work on non-blocking data structures has proposed extend-ing processor designs with a comp...
Abstract. Work on non-blocking data structures has proposed extend-ing processor designs with a comp...
An important class of concurrent objects are those that are non-blocking, that is, whose operations ...
Here, we propose a new approach to design non-blocking algorithms that can apply multiple changes to...
We present a non-blocking lock-free implementation of skip list data structure using multi word comp...
This paper is concerned with system support for nonblocking synchronization in shared-memory multipr...
The number of cores in future multi-core systems are expected to increase by 100 fold over the next ...
The number of cores in future multi-core systems are expected to increase by 100 fold over the next ...
The compare-and-swap register (CAS) is a synchronization primitive for lock-free algorithms. Most us...
Modern computer systems often involve multiple processes or threads of control that communicate thro...
Abstract — We present a new algorithm for implementing a multi-word compare-and-swap functionality s...
Concurrent data structures and algorithms are becoming more relevant with the increase of the number...
Atomic lock-free multi-word compare-and-swap (MCAS) is a powerful tool for designing concurrent algo...
Abstract: "An important class of concurrent objects are those that are lock-free, that is, whose ope...
Algorithms designed for current and future multi-core sys-tems, which are expected to experience an ...
Abstract. Work on non-blocking data structures has proposed extend-ing processor designs with a comp...
Abstract. Work on non-blocking data structures has proposed extend-ing processor designs with a comp...
An important class of concurrent objects are those that are non-blocking, that is, whose operations ...
Here, we propose a new approach to design non-blocking algorithms that can apply multiple changes to...
We present a non-blocking lock-free implementation of skip list data structure using multi word comp...
This paper is concerned with system support for nonblocking synchronization in shared-memory multipr...
The number of cores in future multi-core systems are expected to increase by 100 fold over the next ...
The number of cores in future multi-core systems are expected to increase by 100 fold over the next ...
The compare-and-swap register (CAS) is a synchronization primitive for lock-free algorithms. Most us...
Modern computer systems often involve multiple processes or threads of control that communicate thro...
Abstract — We present a new algorithm for implementing a multi-word compare-and-swap functionality s...
Concurrent data structures and algorithms are becoming more relevant with the increase of the number...
Atomic lock-free multi-word compare-and-swap (MCAS) is a powerful tool for designing concurrent algo...
Abstract: "An important class of concurrent objects are those that are lock-free, that is, whose ope...
Algorithms designed for current and future multi-core sys-tems, which are expected to experience an ...