Common Misconceptions about Saturation Voltage in Nanoscale MOS Transistors

Many undergraduate programs in electronic engineering include a one semester course in semiconductor devices. In this course the student is introduced to lumped physical models that are derived from solid-state physics, statistical mechanics and electrostatics for the operating characteristics of transistors and other semiconductor devices. Among the many concepts taught is that the drain-to-source voltage that causes the current flow in an MOS transistor to saturate ( dsI ∂ / 0Vds → ∂ ) is given by the simple mathematical expression T gsdsat VVV − =. However, this simple expression is widely misapplied by both students and professionals to nanoscale MOS transistors used in modern high-performance microelectronic circuits. This work describes the three competing physical mechanisms that saturate drain-to-source current flow in an MOS transistor and gives a mathematical expression for dsatV for each mechanism