Add to ORKGThis paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called “dynamically variable line-size cache (D-VLS cache)”. The D-VLS cache can optimize its line-size according to the characteristic of programs, and at-tempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is observed that an average memory-access time improvement achieved by a direct-mapped D-VLS cache is about 20 % compared to a conventional direct-mapped cache with fixed 32-byte lines. This performance improvement is better than that of a doubled-size conventional direct-mapped cache†. key words: cache, variable line-size, merged DRAM/logic LSIs, high b...
textContemporary DRAM systems have maintained impressive scaling by managing a careful balance betwe...
This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip m...
Multiple-channel die-stacked DRAMs have been used for maximizing the performance and minimizing the ...
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called ...
This paper proposes a novel cache architecture suit-able for merged DRAM/logic LSIs, which is called...
This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size...
This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size...
Intelligent Memory Systems: Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12...
Integrating main memory (DRAM) and processors into a single chip, or merged DRAM/logic LSI, makes it...
Abstract—The memory bandwidth can dramatically be improved by means of stacking the main memory (DRA...
Die-stacking is a new technology that allows multiple integrated circuits to be stacked on top of ea...
Many of the current memory architectures embed a SRAM cache within the DRAM memory. These architectu...
DRAM caches have shown excellent potential in capturing the spatial and temporal data locality of ap...
DRAMとロジックの混載は, 21世紀のSOC(System-On-a-Chip)時代を支える最も重要な技術の1つである.従来は分チップ構成であったCPUと主記憶を1チップ化することにより, 今までに...
the tight integration of significant quantities of DRAM with high-performance computation logic. How...
textContemporary DRAM systems have maintained impressive scaling by managing a careful balance betwe...
This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip m...
Multiple-channel die-stacked DRAMs have been used for maximizing the performance and minimizing the ...
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called ...
This paper proposes a novel cache architecture suit-able for merged DRAM/logic LSIs, which is called...
This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size...
This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size...
Intelligent Memory Systems: Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12...
Integrating main memory (DRAM) and processors into a single chip, or merged DRAM/logic LSI, makes it...
Abstract—The memory bandwidth can dramatically be improved by means of stacking the main memory (DRA...
Die-stacking is a new technology that allows multiple integrated circuits to be stacked on top of ea...
Many of the current memory architectures embed a SRAM cache within the DRAM memory. These architectu...
DRAM caches have shown excellent potential in capturing the spatial and temporal data locality of ap...
DRAMとロジックの混載は, 21世紀のSOC(System-On-a-Chip)時代を支える最も重要な技術の1つである.従来は分チップ構成であったCPUと主記憶を1チップ化することにより, 今までに...
the tight integration of significant quantities of DRAM with high-performance computation logic. How...
textContemporary DRAM systems have maintained impressive scaling by managing a careful balance betwe...
This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip m...
Multiple-channel die-stacked DRAMs have been used for maximizing the performance and minimizing the ...