This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simulation en-vironment, Embra models the processors of a MIPS R3000/R4000 machine faithfully enough to run a commercial operating system and arbitrary user applications. To achieve high simulation speed, Embra uses dynamic binary translation to generate code sequences which simulate the workload. It is the first machine simulator to use this technique. Embra can simulate real workloads such as multi-process compiles and the SPEC92 benchmarks running on Silicon Graphic’s IRIX 5.3 at speeds only 3 to 9 times slower than native execution of the workload, making Embra the ...
ISBN 978-1-61284-208-0International audienceThis paper presents a strategy to speed-up the simulatio...
Full-system simulators are increasingly finding their way into the consumer space for the purposes o...
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs w...
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocess...
This thesis presents new simulation techniques designed to speed up the simulation of microprocesso...
This paper describes the design and implementation of our high speed simulator for out-of-order micr...
Abstract In recent years multi-core processors have seen broad adoption in application domains rangi...
This paper identifies two challenges that machine simulators such as SimOS must overcome in order to...
Fast computer simulation is an essential tool in the design of large parallel computers. Our Fast Ac...
Fast processor simulators are needed for the software development ofembedded processors, for HW/SW c...
We describe novel techniques used for efficient simulation of memory in SimICS, an instruction leve...
[[abstract]]In recent years, it has gradually become popular to use discrete-event simulation as a t...
We acknowledge funding by the EPSRC grant PAMELA EP/K008730/1.Full-system simulators are increasingl...
This paper introduces SIMinG-1k—a manycore simulator infrastructure. SIMinG-1k is a graphics process...
We describe novel techniques used for efficient simulation of memory in SimICS, an instruction level...
ISBN 978-1-61284-208-0International audienceThis paper presents a strategy to speed-up the simulatio...
Full-system simulators are increasingly finding their way into the consumer space for the purposes o...
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs w...
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocess...
This thesis presents new simulation techniques designed to speed up the simulation of microprocesso...
This paper describes the design and implementation of our high speed simulator for out-of-order micr...
Abstract In recent years multi-core processors have seen broad adoption in application domains rangi...
This paper identifies two challenges that machine simulators such as SimOS must overcome in order to...
Fast computer simulation is an essential tool in the design of large parallel computers. Our Fast Ac...
Fast processor simulators are needed for the software development ofembedded processors, for HW/SW c...
We describe novel techniques used for efficient simulation of memory in SimICS, an instruction leve...
[[abstract]]In recent years, it has gradually become popular to use discrete-event simulation as a t...
We acknowledge funding by the EPSRC grant PAMELA EP/K008730/1.Full-system simulators are increasingl...
This paper introduces SIMinG-1k—a manycore simulator infrastructure. SIMinG-1k is a graphics process...
We describe novel techniques used for efficient simulation of memory in SimICS, an instruction level...
ISBN 978-1-61284-208-0International audienceThis paper presents a strategy to speed-up the simulatio...
Full-system simulators are increasingly finding their way into the consumer space for the purposes o...
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs w...