With the continuing technological trend of ever cheaper and larger memory, most data sets in database servers will soon be able to reside in main memory. In this configuration, the perfor-mance bottleneck is likely to be the gap between the processing speed of the CPU and the memory access latency. Previous work has shown that database applications have large instruction and data footprints and hence do not use processor caches effectively. In this paper, we propose Call Graph Prefetching (CGP), an N instruction prefetching technique that analyzes the call graph of a database system and prefetches instructions from the function that is deemed likely to be called next. CGP capitalizes on the highly predictable function call sequences that ar...
Many modern data processing and HPC workloads are heavily memory-latency bound. A tempting propositi...
CPU speeds double approximately every eighteen months, while main memory speeds double only about ev...
In this dissertation, we provide hardware solutions to increase the efficiency of the cache hierarch...
The large number of cache misses of current applications coupled with the increasing cache miss late...
Data cache misses reduce the performance of wide-issue processors by stalling the data supply to the...
This thesis considers two approaches to the design of high-performance computers. In a <I>single pro...
Recent technological advances are such that the gap between processor cycle times and memory cycle t...
International audienceModern High Performance Computing (HPC) storage systems use heterogeneous stor...
Lookup operations for in-memory databases are heavily memory-bound because they often rely on pointe...
this paper, we examine the way in which prefetching can exploit parallelism. Prefetching has been st...
We present a new hardware-based data prefetching mechanism for enhancing instruction level paralleli...
Abstract. Given the increasing gap between processors and memory, prefetching data into cache become...
Despite rapid increases in CPU performance, the primary obstacles to achieving higher performance in...
A major performance limiter in modern processors is the long latencies caused by data cache misses. ...
As more and more query processing work can be done in main memory, memory access is becoming a signi...
Many modern data processing and HPC workloads are heavily memory-latency bound. A tempting propositi...
CPU speeds double approximately every eighteen months, while main memory speeds double only about ev...
In this dissertation, we provide hardware solutions to increase the efficiency of the cache hierarch...
The large number of cache misses of current applications coupled with the increasing cache miss late...
Data cache misses reduce the performance of wide-issue processors by stalling the data supply to the...
This thesis considers two approaches to the design of high-performance computers. In a <I>single pro...
Recent technological advances are such that the gap between processor cycle times and memory cycle t...
International audienceModern High Performance Computing (HPC) storage systems use heterogeneous stor...
Lookup operations for in-memory databases are heavily memory-bound because they often rely on pointe...
this paper, we examine the way in which prefetching can exploit parallelism. Prefetching has been st...
We present a new hardware-based data prefetching mechanism for enhancing instruction level paralleli...
Abstract. Given the increasing gap between processors and memory, prefetching data into cache become...
Despite rapid increases in CPU performance, the primary obstacles to achieving higher performance in...
A major performance limiter in modern processors is the long latencies caused by data cache misses. ...
As more and more query processing work can be done in main memory, memory access is becoming a signi...
Many modern data processing and HPC workloads are heavily memory-latency bound. A tempting propositi...
CPU speeds double approximately every eighteen months, while main memory speeds double only about ev...
In this dissertation, we provide hardware solutions to increase the efficiency of the cache hierarch...