ADAPTIVE FPGAS: HIGH-LEVEL ARCHITECTURE AND A SYNTHESIS METHOD

This paper presents preliminary work exploring adaptive field programmable gate arrays (AFPGAs). An AFPGA is adap-tative in the sense that the functionality of subcircuits placed on the chip can change in response to changes observed on certain control signals. We describe the high-level architec-ture which adds additional control logic and SRAM bits to a traditional FPGA to produce an AFPGA. We also describe a synthesis method that identifies and resynthesizes mutually exclusive pieces of logic so that they may share the resources available in an AFPGA. The architectural feature and its as-sociated synthesis method helps reduce circuit size by 28% on average and up to 40 % on select circuits. 1