Evaluation of pausible clocking for interfacing high-speed IP cores in GALS systems

Pausible clocking schemes have been proposed by GALS architects as a promising mechanism for reliable data trans-fer between synchronous modules fed by low-speed in-dependent clocks. In this paper, we argue that existing schemes are not well-suited for interfacing high-speed IP cores with large clock-distribution tree delay and high com-munication rates. We propose an alternative interface cir-cuit design for such IP cores that works with partial hand-shake between communicating modules and minimizes the performance penalty of the sender and receiver. Our circuit, unlike pausible clocking, has a small probability of failure.